In memory circuits comprised of cells which are conducting current in a logic "0" state and are not conducting current in a logic "1" state, sense amplifiers are designed to sense current flow for a determination as to whether a logic "1" or a logic "0" is stored by an addressed memory cell. In a conventional memory circuit, the memory cells are arranged in an array established by rows and columns with one memory cell at each intersection of a row and column. A memory cell to be read is coupled to the sense amplifier by coupling the column which contains the memory cell to be read to the sense amplifier via a column decoder. Because such a column has a relatively large capacitance, current flows into the column for some duration even when the memory cell to be read is not conducting current. Consequently there is a delay time before a logic "1" can be detected.
To minimize this delay time, techniques have been developed to rapidly charge the column capacitance with a charging circuit. The charging circuit provides a relatively large amount of current until a first predetermined voltage on the column is reached. A second charge circuit continues to supply current unless a second predetermined voltage is reached at which time a current stops flowing implying the memory cell to be read is in a logic "1" state. If the memory cell to be read is in a logic "0" state, the memory cell conducts sufficient current so that the second charge circuit will not drive the column to the second predetermined voltage. The reason for charging the column to only the second predetermined voltage for detecting a logic "1" is to minimize delay time before being able to detect the next selected memory cell. If the column is charged to a high voltage, the time required to discharge the column can be significant. Historically memories have been designed not only for minimum access time, the time required to make a valid read after receipt of an address, but also for minimum cycle time, the time from a valid read to the next valid read. Consequently, the voltage on the column has been limited to minimize the time required to make the next read.
There are now applications, however, where the cycle time requirement is relatively relaxed compared to the access time requirement. One such situation can be where a memory is on the same semiconductor chip as a microprocessor. In such a case the microprocessor may have a cycle time between addresses which is long compared to that of state of the art memories, but does require a minimum access time from the memory. By taking advantage of the relaxed cycle time requirement, savings in power and chip space can be made over prior art sense amplifiers.
Shown in FIG. 1 is a sense amplifier, operation of which is subsequently described in the body of this specification, of the closest known prior art.